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? semiconductor components industries, llc, 2006 july, 2006 ? rev. 9 1 publication order number: cs5307/d cs5307 four?phase vrm 9.0 buck controller multiphase controllers provide fast, accurate regulation with the control features required to power the next generation of processors in desktop, workstation and server applications. combined with external gate drivers and power components, the cs5307 implements a compact, highly integrated buck converter. enhanced v 2 ? control inherently compensates for variations in both line and load. current sharing between phases is achieved by peak current sharing. the cs5307 includes power good with a programmable lower threshold. applications include embedded processor power and low voltage/high current power supplies. features ? switching regulator controller ? lossless current sensing ? enhanced v 2 control method provides excellent regulation and fast transient response ? programmable 200 to 800 khz switching frequency (per phase) ? duty cycle ? 0% to 100% ? programmable adaptive voltage positioning reduces output capacitor requirements ? programmable soft start ? accurate current sharing ? protection features ? pulse ? by ? pulse current limit for each phase ? programmable hiccup overcurrent protection ? all ?1? dac code fault ? processor overvoltage protection through bottom mosfets ? undervoltage lockout ? system power management ? 5 ? bit dac with 1.0% t olerance compatible with vrm 9.0 ? power good output ? programmable power good lower threshold ? guaranteed startup at ? 20 c pin connections marking diagram a = assembly location wl = wafer lot yy = year ww = work week so ? 24l dw suffix case 751e 1 24 1 cs5307 awlyyww 24 v id1 cs ref v id0 cs4 pwrgds cs3 gate4 cs2 gate3 cs1 gate2 r osc gate1 ocset v cc gnd v id2 v drp v id3 v fb 124 pwrgd ss v id4 comp device package shipping ordering information CS5307GDW24 so ? 24l 30 units/rail cs5307gdwr24 so ? 24l 1000 tape & reel http://onsemi.com
cs5307 http://onsemi.com 2 gnd gate1 gate2 gate3 pwrgds v cc v id0 v id1 v id2 v id3 v id4 pwrgd ocset r osc cs1 cs2 cs3 cs ref ss comp v drp v fb cs5307 pwrgd v id4 v id3 v id2 v id1 v id0 enable v s bg pgnd co bst tg drn enable v s bg pgnd co bst tg drn enable v s bg pgnd co bst tg drn v out +12 v figure 1. application diagram, 12 v to 1.5 v/80 a four ? phase converter cs4 gate4 enable v s bg pgnd co bst tg drn ncp5351 ncp5351 ncp5351 ncp5351 gnd 6.2 v 5.5 v
cs5307 http://onsemi.com 3 maximum ratings* rating value unit operating junction temperature 150 c storage temperature range ? 65 to 150 c esd susceptibility (human body model) 2.0 kv package thermal resistance junction ? to ? case, r jc junction ? to ? ambient, r ja 16 80 c/w c/w lead temperature soldering: reflow (note 1.) 230 peak c msl level 1 ? 1. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. maximum ratings pin number pin symbol v max v min i source i sink 1 gnd n/a n/a 0.4 a, 1.0 s, 100 ma dc n/a 2 ocset 7.0 v ? 0.3 v 1.0 ma 1.0 ma 3 r osc 7.0 v ? 0.3 v 1.0 ma 1.0 ma 4 ? 7 cs1 ? cs4 7.0 v ? 0.3 v 1.0 ma 1.0 ma 8 cs ref 7.0 v ? 0.3 v 1.0 ma 1.0 ma 9 v drp 7.0 v ? 0.3 v 1.0 ma 1.0 ma 10 v fb 7.0 v ? 0.3 v 1.0 ma 1.0 ma 11 comp 7.0 v ? 0.3 v 1.0 ma 1.0 ma 12 ss 7.0 v ? 0.3 v 1.0 ma 1.0 ma 13 pwrgd 18 v ? 0.3 v 1.0 ma 10 ma 14 pwrgds 7.0 v ? 0.3 v 1.0 ma 1.0 ma 15 ? 19 v id4 ? v id0 18 v ? 0.3 v 1.0 ma 1.0 ma 20 ? 23 gate4 ? gate1 7.0 v ? 0.3 v 0.1 a, 1.0 s, 25 ma dc 0.1 a, 1.0 s, 25 ma dc 24 v cc 18 v ? 0.3 v 100 ma 1.0 ma
cs5307 http://onsemi.com 4 electrical characteristics (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 32.4 k , v ocset = 0.54 v, dac code 01110; unless otherwise stated.) parameter test conditions min typ max unit voltage identification dac (0 = connected to gnd, 1 = open or pull ? up to internal 3.3 v or external voltage 12 v) accuracy (all codes) v id code connect v fb to comp, measure comp ? 1.0 ? +1.0 % v id4 v id3 v id2 v id1 v id0 1 1 1 1 1 fault 1 1 1 1 0 1.089 1.100 1.111 v 1 1 1 0 1 1.114 1.125 1.136 v 1 1 1 0 0 1.139 1.150 1.162 v 1 1 0 1 1 1.163 1.175 1.187 v 1 1 0 1 0 1.188 1.200 1.212 v 1 1 0 0 1 1.213 1.225 1.237 v 1 1 0 0 0 1.238 1.250 1.263 v 1 0 1 1 1 1.263 1.275 1.288 v 1 0 1 1 0 1.287 1.300 1.313 v 1 0 1 0 1 1.312 1.325 1.338 v 1 0 1 0 0 1.337 1.350 1.364 v 1 0 0 1 1 1.361 1.375 1.389 v 1 0 0 1 0 1.386 1.400 1.414 v 1 0 0 0 1 1.411 1.425 1.439 v 1 0 0 0 0 1.436 1.450 1.465 v 0 1 1 1 1 1.460 1.475 1.490 v 0 1 1 1 0 1.485 1.500 1.515 v 0 1 1 0 1 1.510 1.525 1.540 v 0 1 1 0 0 1.535 1.550 1.566 v 0 1 0 1 1 1.560 1.575 1.591 v 0 1 0 1 0 1.584 1.600 1.616 v 0 1 0 0 1 1.609 1.625 1.641 v 0 1 0 0 0 1.634 1.650 1.667 v 0 0 1 1 1 1.658 1.675 1.692 v 0 0 1 1 0 1.683 1.700 1.717 v 0 0 1 0 1 1.708 1.725 1.742 v 0 0 1 0 0 1.733 1.750 1.768 v 0 0 0 1 1 1.757 1.775 1.793 v 0 0 0 1 0 1.782 1.800 1.818 v 0 0 0 0 1 1.807 1.825 1.843 v 0 0 0 0 0 1.832 1.850 1.869 v input threshold v id4 , v id3 , v id2 , v id1 , v id0 1.00 1.25 1.5 v input pull ? up resistance 0 v < v id4 , v id3 , v id2 ,v id1 , v id0 < 3.3 v 25 50 100 k
cs5307 http://onsemi.com 5 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 32.4 k , v ocset = 0.54 v, dac code 01110; unless otherwise stated.) parameter unit max typ min test conditions voltage identification dac (0 = connected to gnd, 1 = open or pull ? up to internal 3.3 v or external voltage 12 v) (continued) pull ? up voltage 1.0 m to gnd 2.5 2.7 3.0 v power good output upper threshold force pwrgds 1.876 ( ? 5%) 1.975 2.074 (+5%) v lower threshold force pwrgds ? 5% v id /2 +5% v switch leakage current v cc = 14 v, pwrgds = 1.4 v ? 0.1 1.0 a delay pwrgds low to pwrgd low 100 800 2000 s output low voltage pwrgds = 1.0 v, i pwrgd = 4.0 ma ? 0.15 0.4 v voltage feedback error amplifier v fb bias current note 2 9.9 10.25 10.6 a comp source current comp = 0.5 v to 2.0 v, v fb = 1.8 v, dac = 00000 15 30 60 a comp sink current comp = 0.5 v to 2.0 v, v fb = 1.15 v, dac = 11110 15 30 60 a transconductance ? 10 a < i comp < +10 a, note 3 200 500 750 mho output impedance ? ? 2.5 ? m open loop dc gain note 3 45 95 ? db unity gain bandwidth ? ? 50 ? khz psrr @ 1.0 khz ? ? 60 ? db comp max voltage v fb = 0 v 2.4 2.7 ? v comp min voltage v fb = 1.6 v ? 50 150 mv pwm comparators minimum pulse width measured from csx to gatex, v fb = cs ref = 0.5 v, comp = 0.5 v, 60 mv step on csx; measure at gatex = 1.0 v ? 40 70 ns transient response time measured from cs ref to gatex, comp = 2.1 v, csx = cs ref = 0.5 v, cs ref stepped from 1.2 v ? 2.0 v ? 40 60 ns channel start ? up offset csx = cs ref = v fb = 0 v, measure v comp when gatex switch high 350 600 750 mv artificial ramp amplitude 50% duty cycle, note 3 ? 115 ? mv gates high voltage measure gatex i gatex = 1.0 ma 2.0 2.6 3.0 v low voltage measure gatex, i gatex = 1.0 ma ? 0.5 0.7 v 2. the v fb bias current changes with the value of r osc per figure 4. 3. guaranteed by design. not tested in production.
cs5307 http://onsemi.com 6 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 32.4 k , v ocset = 0.54 v, dac code 01110; unless otherwise stated.) parameter unit max typ min test conditions gates rise time 0.8 v < gatex < 2.0 v, v cc = 10 v ? 5.0 20 ns fall time 2.0 v > gatex > 0.8 v, v cc = 10 v ? 5.0 20 ns oscillator switching frequency r osc = 32.4 k 300 400 500 khz switching frequency r osc = 63.4 k , note 4 150 200 250 khz switching frequency r osc = 16.2 k , note 4 600 800 1000 khz r osc voltage 0.90 1.00 1.10 v phase delay ? 75 90 105 deg adaptive voltage positioning v drp output voltage to dac out offset csx = cs ref , v fb = comp, measure v drp ? comp ? 5.0 0 5.0 mv maximum v drp voltage csx ? cs ref = 50 mv, v fb = comp, t a = 25 c, measure v drp ? comp 500 555 610 mv current sense input to v drp gain csx ? cs ref = 50 mv, v fb = comp, t a = 25 c, measure v drp ? comp 2.5 2.78 3.05 v/v temperature coefficient of v drp gain (v@temp v@room) 10 6 t v@room ? ? 685 ? ppm/ c v drp source current limit csx ? cs ref = 50 mv, v fb = comp, measure v drp ? comp v drp = 1.5 v 1.0 7.0 14 ma soft start ss source current v cc = 10 v 130 160 200 a ss sink current v cc = 7.0 v 4.0 5.0 6.25 a ss min threshold v cc = 10 v 0.25 0.3 0.35 v ss max threshold v cc = 10 v 2.4 2.7 ? v ss source/sink ratio ? 20 32 48 ? ss comp pull down current v cc = 10 v 200 900 3000 a current sense amplifiers cs ref input bias current cs ref = csx = 0 v ? 3.4 4.0 a csx input bias current cs ref = csx = 0 v ? 0.1 1.0 a sense amp gain cs ref = 0 v, csx = 0.05 v, measure v(comp) when gatex switches high ? 2.65 ? v/v common mode input range note 4 0 ? 2.0 v bandwidth ? ? 7.0 ? mhz single phase pulse by pulse current limit v fb = cs ref = 0.5 v, comp = 2.0 v, measure csx ? cs ref when gatex goes low 75 85 100 mv 4. guaranteed by design. not tested in production.
cs5307 http://onsemi.com 7 electrical characteristics (continued) (0 c < t a < 70 c; 0 c < t j < 125 c; 9.5 v < v cc < 14 v; c gatex = 100 pf, c comp = 0.01 f, c ss = 0.1 f, c vcc = 0.1 f, r rosc = 32.4 k , v ocset = 0.54 v, dac code 01110; unless otherwise stated.) parameter unit max typ min test conditions current sense amplifiers ocset input bias current ocset = 0 v ? 0.1 1.0 a current sense input to ocset gain ocset/(csx ? cs ref ), 0.25 v < ocset < 0.6 v, gatex not switching 2.5 2.8 3.1 v/v current limit filter slew rate cs ref = 1.1 v, csx = 1.0 v, pulse csx to 1.16 v, note 5. 2.0 5.0 13 mv/ s general electrical specification v cc operating current comp = 0.3 v (no switching) ? 20 30 ma uvlo start threshold ss charging gates switching 8.5 9.0 9.5 v uvlo stop threshold gates not switching, ss & comp discharging 7.5 8.0 8.5 v uvlo hysteresis start ? stop 0.8 1.0 1.2 v 5. guaranteed by design. not tested in production. package pin description pin number pin symbol pin name function 1 gnd ground ic power supply return. connected to ic substrate. 2 ocset overcurrent set resistor divider from r osc to gnd. programs the threshold of the hiccup overcurrent protection. 3 r osc oscillator frequency adjust r osc is a regulated 1.0 v output and programs the oscillator frequency with a resistor to gnd. 4 ? 7 cs1 ? cs4 current sense inputs non ? inverting inputs to the current sense amplifiers. 8 cs ref current sense reference inverting input to the current sense amplifiers and reference for power good. 9 v drp current sense amp output programs the voltage drop due to loading. a resistor from v drp to fb programs the amount of adaptive voltage positioning. omitting this resistor defeats the avp function. 10 v fb voltage feedback error amplifier inverting input. input bias current is used to program avp light load offset via a resistor connected to the converter output voltage. 11 comp error amp output and pwm comparator input provides loop compensation and is clamped by ss. 12 ss soft start controls fault timing and startup. 13 pwrgd power good output open collector output, which is ?low? when the converter output is out of regulation. 14 pwrgds power good sense a resistor divider from v out to gnd programs the power good lower threshold. 15 ? 19 v id4 ? v id0 dac v id inputs ttl ? compatible logic input used to program the converter output voltage. internal 50 k pull ? ups to 3.3 v via a blocking diode are provided. all high generates fault. 20 ? 23 gate4 ? 1 channel outputs pwm outputs to drive fet driver ic. 24 v cc supply input ic bias input.
cs5307 http://onsemi.com 8 figure 2. block diagram ibias v id0 v id1 v id2 v id3 v id4 dac 50 k ? + 3.3 v ocset dac output vid = 11111 ? oc filter ? + start stop ? + v cc 9.0 v 8.0 v uvlo comparator ? + ? + ? + 0.3 v discharge comparator set dominant s r * 0.5 v ? + ? + v drp ? + ? + pwm1 comparator ilim1 comparator ? + 0.33 v co1 co1f ? + ? + pwm2 comparator ilim2 comparator ? + 0.33 v co2 co2f ? + ? + pwm3 comparator ilim3 comparator ? + 0.33 v co3 co3f reset dominant r s reset dominant r s reset dominant r s v cc v cc gate2 gate1 gate3 latch pwm1 latch pwm2 latch pwm3 ? + avp amp delay ? + ? + 1.975 v pwrgd ? 4 co1 2.65 co1f 4 co2 co2f 4 co3 co3f ? + ? + ? + ? + ? + cs ref cs1 cs2 cs3 ? + ? + ss ? + v fb 0.6 v comp current source generator ? + 1.0 v ? + r osc pulseout1 pulseout2 pulseout3 iosc oscillator gnd fault oc comparator v cc ? + ? + pwm4 comparator ilim4 comparator ? + 0.33 v co4 co4f reset dominant r s v cc gate4 latch pwm4 pulseout4 cs4 ? + co4 co4f ? + 4 160 a 5.0 a 3.3 v ramp1 ramp2 ramp3 ramp4 art ramp 4 art ramp 3 art ramp 2 art ramp 1 soft start latch * 0.75 v pwrgds 3.3 v 2.65 2.65 2.65
cs5307 http://onsemi.com 9 typical performance characteristics figure 3. oscillator frequency frequency (khz) 100 r osc value (k ) 300 400 500 600 700 800 900 200 10 20 30 40 50 60 70 10 v fb bias current ( a) 0 r osc value (k ) 5 10 15 20 25 20 30 40 50 60 70 80 figure 4. v fb bias current vs. r osc value 0 f osc (khz) 401 t a ( c) 404 405 406 407 408 409 410 20 40 60 80 100 120 402 403 figure 5. i cc vs. temperature figure 6. oscillator frequency vs. temperature (r osc = 32.4 k ) 0 i cc (ma) 18 t a ( c) 19 20 21 22 23 24 20 40 60 80 100 120 0 error (%) ? 0.05 t a ( c) 0.00 0.05 0.10 0.15 0.20 20 40 60 80 100 120 vid = 1.1 v vid = 1.3 v vid = 1.5 v 0 offset voltage (mv) 300 t a ( c) 400 450 500 550 600 650 700 20 40 60 80 100 120 350 figure 7. dac output error vs. temperature figure 8. current sense amplifier channel startup offset voltage vs. temperature
cs5307 http://onsemi.com 10 typical performance characteristics figure 9. sense amp gains vs. temperature figure 10. power good delay vs. temperature figure 11. v drp to dac output offset voltage vs. temperature figure 12. v drp source current vs. temperature figure 13. v fb bias currents vs. temperature (r osc = 32.4 k ) 0 gain (v/v) 2.2 t a ( c) 2.3 2.4 2.5 2.6 2.7 2.8 2.9 20 40 60 80 100 120 current sense amp to oc comparator current sense amp to v drp gain current sense amp to pwm comparator 0 offset voltage (mv) ? 0.8 t a ( c) ? 0.3 ? 0.2 ? 0.1 0.0 0.1 0.2 0.3 20 40 60 80 100 120 ? 0.7 ? 0.6 ? 0.5 ? 0.4 0 v drp source current (ma) ? 3.80 t a ( c) ? 3.75 ? 3.70 ? 3.65 ? 3.60 ? 3.55 20 40 60 80 100 120 0 v fb bias current ( a) 10.18 t a ( c) 10.20 10.22 10.24 10.26 10.28 10.30 20 40 60 80 100 120 v fb = 1.9 v v fb = 1.0 v power good delay (ms) 0.60 0.70 0.75 0.80 0.85 0.90 0.95 1.00 0.65 0 t a ( c) 20 40 60 80 100 120
cs5307 http://onsemi.com 11 applications information overview the cs5307 dc/dc controller from on semiconductor was developed using the enhanced v 2 topology. enhanced v 2 combines the original v 2 topology with peak current ? mode control for fast transient response and current sensing capability. the addition of an internal pwm ramp and implementation of fast ? feedback directly from vcore has improved transient response and simplified design. the cs5307 includes power good (pwrgd), providing a highly integrated solution to simplify design, minimize circuit board area, and reduce overall system cost. two advantages of a multi ? phase converter over a single ? phase converter are current sharing and increased apparent output frequency. curre nt sharing allows the designer to use less inductance in each phase than would be required in a single ? phase converter. the smaller inductor will produce larger ripple currents but the total per ? phase power dissipation is reduced because the rms current is lower. transient response is improved because the control loop will measure and adjust the current faster in a smaller output inductor. increased apparent output frequency is desirable because the off ? time and the ripple voltage of the multi ? phase converter will be less than that of a single ? phase converter. fixed frequency multi ? phase control in a multi ? phase converter, multiple converters are connected in parallel and are switched on at different times. this reduces output current from the individual converters and increases the apparent ripple frequency. because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components. the cs5307 controller uses four ? phase, fixed ? frequency, enhanced v 2 architecture to measure and control currents in individual phases. each phase is delayed 90 from the previous phase. normally, gatex transitions to a high voltage at the beginning of each oscillator cycle. inductor current ramps up until the combination of the current sense signal, the internal ramp and the output voltage ripple trip the pwm comparator and bring gatex low. once gatex goes low, it will remain low until the beginning of the next oscillator cycle. while gatex is high, the enhanced v 2 loop will respond to line and load variations. on the other hand, once ga tex is low, the loop cannot respond until the beginning of the next pwm cycle. therefore, constant frequency enhanced v 2 will typically respond to disturbances within the off ? time of the converter. the enhanced v 2 architecture measures and adjusts the output current in each phase. an additional input (csx) for inductor current information has been added to the v 2 loop for each phase as shown in figure 14. the triangular inductor current is measured differentially across rs, amplified by csa and summed with the channel startup offset, the internal ramp and the output voltage at the non ? inverting input of the pwm comparator. the purpose of the internal ramp is to compensate for propagation delays in the cs5307. this provides greater design flexibility by allowing smaller external ramps, lower minimum pulse widths, higher frequency operation and pwm duty cycles above 50% without external slope compensation. as the sum of the inductor current and the internal ramp increase, the voltage on the positive pin of the pwm comparator rises and terminates the pwm cycle. if the inductor starts a cycle with higher current, the pwm cycle will terminate earlier providing negative feedback. the cs5307 provides a csx input for each phase, but the cs ref and comp inputs are common to all phases. current sharing is accomplished by referencing all phases to the same cs ref and comp pins, so that a phase with a lar ger current signal will turn off earlier than a phase with a smaller current signal. figure 14. enhanced v 2 control employing resistive current sensing and internal ramp + ? swnode lx rlx rsx csx csa cox cs ref + v out (v core ) + ? ?fast ? feedback? connection + ? pwm comp to f/f reset channel start ? up offset ? + e.a. dac out v fb comp internal ramp + x = 1, 2, 3, or 4
cs5307 http://onsemi.com 12 enhanced v 2 responds to disturbances in v core by employing both ?slow? and ?fast? voltage regulation. the internal error amplifier performs the slow regulation. depending on the gain and frequency compensation set by the amplifier?s external components, the error amplifier will typically begin to ramp its output to react to changes in the output voltage in one or two pwm cycles. fast voltage feedback is implemented by a direct connection from vcore to the non ? inverting pin of the pwm comparator via the summation with the inductor current, internal ramp and offset. a rapid increase in output current will produce a negative offset at vcore and at the output of the summer. this will cause the pwm duty cycle to increase almost instantly. fast feedback will typically adjust the pwm duty cycle in one pwm cycle. as shown in figure 14, an internal ramp (nominally 115 mv at a 50% duty cycle) is added to the inductor current ramp at the positive terminal of the pwm comparator. this additional ramp compensates for propagation time delays from the current sense amplifier (csa), the pwm comparator and the mosfet gate drivers. as a result, the minimum on time of the controller is reduced and lower duty ? cycles may be achieved at higher frequencies. also, the additional ramp reduces the reliance on the inductor current ramp and allows greater flexibility when choosing the output inductor and the r csx c csx time constant of the feedback components from v core to the csx pin. including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. when the average output current is zero, the comp pin will be: v comp v out @0a channel_startup_offset int_ramp g csa ext_ramp 2 int_ramp is the ?partial? internal ramp value at the corresponding duty cycle, ext_ramp is the peak ? to ? peak external steady ? state ramp at 0 a, g csa is the current sense amplifier gain (nominally 2.65 v/v) and the channel startup offset is typically 0.60 v. the magnitude of the ext_ramp can be calculated from: ext_ramp d (v in v out ) (r csx c csx f sw ) for example, if v out at 0 a is set to 1.700 v with avp and the input voltage is 12.0 v, the duty cycle (d) will be 1.700/12.0 or 14.2%. int_ramp will be 115 mv/50% ? 14.2% = 33 mv. realistic values for r csx , c csx and f sw are 10 k , 0.015 f and 650 khz. using these and the previously mentioned formula, ext_ramp will be 15.0 mv. v comp 1.700 v 0.60 v 33 mv 2.65 v v 15.0 mv 2 2.353 vdc. if the comp pin is held steady and the inductor current changes, there must also be a change in the output voltage. or, in a closed loop configuration when the output current changes, the comp pin must move to keep the same output voltage. the required change in the output voltage or comp pin depends on the scaling of the current feedback signal and is calculated as: v r s g csa i out the single ? phase power stage output impedance is: single stage impedance v out i out r s g csa the total output impedance will be the single stage impedance divided by 4. the output impedance of the power stage determines how the converter will respond during the first few microseconds of a transient before the feedback loop has repositioned the comp pin. the peak output current can be calculated from: i out,peak ( v co mp v ou t offset ) ( r s g cs a ) figure 15 shows the step response of the comp pin at a fixed level. before t1, the converter is in normal steady ? state operation. the inductor current provides a portion of the pwm ramp through the current sense amplifier. the pwm cycle ends when the sum of the current ramp, the ?partial? internal ramp voltage signal and offset exceed the level of the comp pin. at t1, the output current increases and the output voltage sags. the next pwm cycle begins and the cycle continues longer than previously while the current signal increases enough to make up for the lower voltage at the v fb pin and the cycle ends at t2. after t2, the output voltage remains lower than at light load and the average current signal level (csx output) is raised so that the sum of the current and voltage signal is the same as with the original load. in a closed loop system, the comp pin would move higher to restore the output voltage to the original level. swnode v fb (v out ) internal ramp csa out w/ exaggerated delays comp ? offset csa out + ramp + cs ref t1 t2 figure 15. open loop operation
cs5307 http://onsemi.com 13 figure 16. enhanced v 2 control employing lossless inductive current sensing and internal ramp + ? swnode lx r csx rlx csx csa cox cs ref + v out (v core ) ?fast ? feedback? connection + ? pwm comp to f/f reset channel start ? up offset ? + e.a. dac out v fb comp internal ramp + x = 1, 2, 3, or 4 c csx + ? inductive current sensing for lossless sensing, current can be sensed across the inductor as shown in figure 16. in the diagram, l is the output inductance and r l is the inherent inductor resistance. to compensate the current sense signal, the values of r csx and c csx are chosen so that l/r l = r csx ? c csx . if this criteria is met, the current sense signal will be the same shape as the inductor current and the voltage signal at csx will represent the instantaneous value of inductor current. also, the circuit can be analyzed as if a sense resistor of value r l was used. when choosing or designing inductors for use with inductive sensing, tolerances and temperature effects should be considered. cores with a low permeability material or a large gap will usually have minimal inductance change with temperature and load. copper magnet wire has a temperature coefficient of 0.39% per c. the increase in winding resistance at higher temperatures should be considered when setting the ocset threshold. if a more accurate current sense is required than inductive sensing can provide, current can be sensed through a resistor as shown in figure 14. current sharing accuracy printed circuit board (pcb) traces that carry inductor current can be used as part of the current sense resistance depending on where the current sense signal is picked off. for accurate current sharing, the current sense inputs should sense the current at relatively the same point for each phase and the connection to the cs ref pin should be made so that no phase is favored. in some cases, especially with inductive sensing, resistance of the pcb can be useful for increasing the current sense resistance. the total current sense resistance used for calculations must include any pcb trace resistance between the csx input and the cs ref input that carries inductor current. current sense amplifier (csa) input mismatch and the value of the current sense component will determine the accuracy of the current sharing between phases. the worst case csa input mismatch is 10 mv and will typically be within 4.0 mv. the difference in peak currents between phases will be the csa input mismatch divided by the current sense resistance. if all current sense components are of equal resistance, a 3.0 mv mismatch with a 2.0 m sense resistance will produce a 1.5 a difference in current between phases. external ramp size and current sensing the internal ramp allows flexibility in setting the current sense time constant. t ypically, the current sense r csx ? c csx time constant should be equal to or slightly slower than the inductor?s time constant. if rc is chosen to be smaller (faster) than l/r l , the ac or transient portion of the current sensing signal will be scaled larger than the dc portion. this will provide a larger steady ? state ramp, but circuit performance will be affected and must be evaluated carefully. the current signal will overshoot during transients and settle at the rate determined by r csx ? c csx . it will eventually settle to the correct dc level, but the error will decay with the time constant of r csx ? c csx . if this error is excessive, it will affect transient response, adaptive positioning and current limit. during a positive current transient, the comp pin will be required to undershoot in response to the current signal in order to maintain the output voltage. similarly, the v drp signal will overshoot which will produce too much transient droop in the output voltage. the single ? phase pulse ? by ? pulse overcurrent protection will trip earlier than it would if compensated correctly and hiccup ? mode current limit will have a lower threshold for fast rising step loads than for slowly rising output currents. the waveforms in figure 17 show a simulation of the current sense signal and the actual inductor current during a positive step in load current with values of l = 500 nh, r l = 1.6 m , r csx = 20 k and c csx = .01 f. in this case, ideal current signal compensation would require r csx to be 31 k .
cs5307 http://onsemi.com 14 due to the faster than ideal rc time constant, there is an overshoot of 50% and the overshoot decays with a 200 s time constant. with this compensation, the ocset pin threshold must be set more than 50% above the full load current to avoid triggering current limit during a large output load step. transient response and adaptive voltage positioning for applications with fast transient currents, the output filter is frequently sized larger than ripple currents require in order to reduce voltage excursions during load transients. adaptive voltage positioning can reduce peak ? peak output voltage deviations during load transients and allow for a smaller output filter. the output voltage can be set higher than nominal at light loads to reduce output voltage sag when the load current is applied. similarly, the output voltage can be set lower than nominal during heavy loads to reduce overshoot when the load current is removed. for low current applications, a droop resistor can provide fast, accurate adaptive positioning. however, at high currents, the loss in a droop resistor becomes excessive. for example, a 50 a converter with a 1 m resistor would provide a 50 mv change in output voltage between no load and full load and would dissipate 2.5 w. lossless adaptive voltage positioning (avp) is an alternative to using a droop resistor, but it must respond to changes in load current. figure 18 shows how avp works. the waveform labeled ?normal? shows a converter without avp. on the left, the output voltage sags when the output current is stepped up and later overshoots when current is stepped back down. with fast (ideal) avp, the peak ? to ? peak excursions are cut in half. in the slow avp waveform, the output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. the controller can be configured to adjust the output voltage based on the output current of the converter. (refer to the application diagram in figure 1). to set the no ? load positioning, a resistor is placed between the output voltage and v fb pin. the v fb bias current will develop a voltage across the resistor to adjust the no ? load output voltage. the v fb bias current is dependent on the value of r osc as shown in the datasheets. during no ? load conditions, the v drp pin is at the same voltage as the v fb pin, so none of the v fb bias current flows through the v drp resistor. when output current increases, the v drp pin voltage increases proportionally. current set by the v drp resistor offsets the v fb bias current, causing the output voltage to decrease. the response during the first few microseconds of a load transient is controlled primarily by power stage output impedance, and by the esr and esl of the output filter. the transition between fast and slow positioning is controlled by the total ramp size and the error amp compensation. if the ramp size is too large or the error amp too slow, there will be a long transition to the final voltage after a transient. this will be most apparent with low capacitance output filters. figure 17. inductive sensing waveform during a load step with fast rc time constant (50 s/div) adaptive positioning adaptive positioning normal fast slow limits figure 18. adaptive voltage positioning overvoltage protection overvoltage protection (ovp) is provided as a result of the normal operation of the enhanced v 2 control topology with synchronous rectifiers. the control loop responds to an overvoltage condition within 40 ns, causing the gatex output to shut off. the (external) mosfet driver should react normally to turn off the top mosfet and turn on the bottom mosfet. this results in a ?crowbar? action to clamp the output voltage and prevent damage to the load. the regulator will remain in this state until the overvoltage condition ends or the input voltage is pulled low. power good according to the latest specifications, the power good (pwrgd) signal must be asserted when the output voltage is within a window defined by the vid code, as shown in figure 19. the pwrgds pin is provided to allow the pwrgd comparators to accurately sense the output voltage. the effect of the pwrgd lower threshold can be modified using a resistor divider from the output to pwrgds to ground, as shown in figure 20.
cs5307 http://onsemi.com 15 pwrgd ??? ??? ??? ??? ??? ??? ??? ??? ? 5.0% +5.0% ? 5.0% +5.0% figure 19. pwrgd assertion window low pwrgd low pwrgd high figure 20. adjusting the pwrgd threshold v out r1 r2 pwrgds since the internally ? set thresholds for pwrgds are vid/2 for the lower threshold and a fixed 1.975v for the upper threshold, a simple equation can be provided to assist the designer in selecting a resistor divider to provide the desired pwrgd performance. v lower v vid 2 r 1 r 2 r 1 v upper 1.975 v the logic circuitry inside the chip sets pwrgd low only after a delay period has been passed. a ?power bad? event does not cause pwrgd to go low unless it is sustained through the delay time of 500 s. if the anomaly disappears before the end of the delay, the pwrgd output will never be set low. in order to use the pwrgd pin as specified, the user is advised to connect external resistors as necessary to limit the current into this pin to 4 ma or less. undervoltage lockout the cs5307 includes an undervoltage lockout circuit. this circuit keeps the ic?s output drivers low until v cc applied to the ic reaches 9 v. the gate outputs are disabled when v cc drops below 8 v. soft start and hiccup mode at initial power ? up, both ss and comp voltages are zero. the total ss capacitance will begin to charge with a current of 160 a. the error amplifier directly charges the comp capacitance. an internal clamp ensures that the comp pin voltage will always be less than the voltage at the ss pin, ensuring proper start ? up behavior. all gate outputs are held low until the comp voltage reaches 0.6 v. once this threshold is reached, the gate outputs are released to operate normally. in current limit, the internal fault latch will initiate a 5 a discharge current on the ss pin, and the internal clamp will discharge the capacitor connected to the comp pin at a similar rate. this performance will result in gate pulses being generated until the overcurrent condition reoccurs and the discharge/soft start cycle begins anew. current limit two levels of over ? current protection are provided. first, if the voltage on the current sense pins (csx) exceeds cs ref by more than a fixed threshold (single pulse current limit), the pwm comparator is turned off. this provides fast peak current protection for individual phases. second, the individual phase currents are summed and low ? pass filtered to compare an averaged current signal to a user adjustable voltage on the ocset pin. if the ocset voltage is exceeded, the fault latch trips and the soft start capacitor discharges until the soft start pin reaches 0.3 v. then soft start begins. the converter will continue to operate in a low average current hiccup ? mode until the fault condition is corrected. fault protection logic the cs5307 includes fault protection circuitry to prevent harmful modes of operation from occurring. the fault logic is described in table 1. gate outputs the cs5307 is designed to operate with external gate drivers. accordingly, the gate outputs are capable of driving a 100 pf load with typical rise and fall times of 5 ns. digital to analog converter (dac) the output voltage of the cs5307 is set by means of a 5 ? bit, 1% dac. the dac pins are internally pulled up to a 3.3 v rail through a blocking diode and a set of 50 k resistors. the blocking diode allows external pull up to a bias voltage greater than 3.3 v and less than 13 v. the output of the dac is described in the electrical characteristics section of the data sheet. these outputs are consistent with the latest vrm and processor specifications. the dac output is equal to the vid code specification. in order to produce a workable power supply using the cs5307, the designer is expected to use avp as described earlier to position the output voltage above the dac output, resulting in an output voltage somewhere in the middle of the acceptable range.
cs5307 http://onsemi.com 16 table 1. fault protection logic fault modes stop switching ss pin characteristics reset method undervoltage lockout yes ? 5.0 a ss < 0.3 v vid ? 11111 yes ? 5.0 a change vid code phase over current (0.33 v limit) no not affected automatic the latest vrm and processor specifications require a power supply to turn its output off in the event of a 1 1111 vid code. when the dac sees such a code, the gate pins stop switching and go low. this condition is described in table 1. design procedure 1. output capacitor selection the output capacitors filter the current from the output inductor and provide a low impedance for transient load current changes. typically, microprocessor applications require both bulk (electrolytic, tantalum) and low impedance, high frequency (ceramic) types of capacitors. the bulk capacitors provide ?hold up? during transient loading. the low impedance capacitors reduce steady ? state ripple and bypass the bulk capacitance when the output current changes very quickly. the microprocessor manufacturers usually specify a minimum number of ceramic capacitors. the designer must determine the number of bulk capacitors. choose the number of bulk output capacitors to meet the peak transient requirements. the formula below can be used to provide a starting point for the minimum number of bulk capacitors (n out,min ): n out,min esr per capacitor i o,max v o,max (1) in reality, both the esr and esl of the bulk capacitors determine the voltage change during a load transient according to: v o , max ( i o , max t) esl i o , max esr (2) unfortunately, capacitor manufacturers do not specify the esl of their components and the inductance added by the pcb traces is highly dependent on the layout and routing. therefore, it is necessary to start a design with slightly more than the minimum number of bulk capacitors and perform transient testing or careful modeling/simulation to determine the final number of bulk capacitors. 2. output inductor selection the output inductor may be the most critical component in the converter because it will directly effect the choice of other components and dictate both the steady ? state and transient performance of the converter. when selecting an inductor, the designer must consider factors such as dc current, peak current, output voltage ripple, core material, magnetic saturation, temperature, physical size and cost (usually the primary concern). in general, the output inductance value should be elecrrically and physically as small as possible to provide the best transient response at minimum cost. if a large inductance value is used, the converter will not respond quickly to rapid changes in the load current. on the other hand, too low an inductance value will result in very large ripple currents in the power components (mosfets, capacitors, etc.) resulting in increased dissipation and lower converter efficiency. increased ripple currents force the designer to use higher rated mosfets, oversize the thermal solution, and use more, higher rated input and output capacitors, adversely affecting converter cost. one method of calculating an output inductor value is to size the inductor to produce a specified maximum ripple current in the inductor. lower ripple currents will result in less core and mosfet losses and higher converter efficiency. equation 3 may be used to calculate the minimum inductor value to produce a given maximum ripple current ( ) per phase. the inductor value calculated by this equation is a minimum because values less than this will produce more ripple current than desired. conversely, higher inductor values will result in less than the selected maximum ripple current. lo min (v in v out ) v out ( i o,max v in f sw ) (3) is the ripple current as a percentage of the maximum output current per phase ( = 0.15 for 15%, = 0.25 for 25%, etc.). if the minimum inductor value is used, the inductor current will swing % about its value at the center. therefore, for a four ? phase converter, the inductor must be designed or selected such that it will not saturate with a peak current of (1 + ) ? i o,max /4. the maximum inductor value is limited by the transient response of the converter. if the converter is to have a fast transient response, the inductor should be made as small as possible. if the inductor is too large its current will change too slowly, the output voltage will droop excessively, more bulk capacitors will be required and the converter cost will be increased. for a given inductor value, it is useful to determine the times required to increase or decrease the current. for increasing current: t inc lo i o (v in v out ) (3.1)
cs5307 http://onsemi.com 17 for decreasing current: t dec lo i o (v out ) (3.2) for typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. thus, it may be more dif ficult for the converter to stay within the regulation limits when the load is removed than when it is applied and excessive overshoot may result. the output voltage ripple can be calculated using the output inductor value derived in this section (lo min ), the number of output capacitors (n out,min ) and the per capacitor esr determined in the previous section: v out,p ? p (esr per cap n out,min ) (v in #phases v out ) d (lo min f sw ) (4) this formula assumes steady ? state conditions with no more than one phase on at any time. the second term in equation 4 is the total ripple current seen by the output capacitors. the total output ripple current is the ?time summation? of the four individual phase currents that are 90 degrees out ? of ? phase. as the inductor current in one phase ramps upward, current in the other phase ramps downward and provides a canceling of currents during part of the switching cycle. therefore, the total output ripple current and voltage are reduced in a multi ? phase converter. 3. input capacitor selection the choice and number of input capacitors is primarily determined by their voltage and ripple current ratings. the designer must choose capacitors that will support the worst case input voltage with adequate margin. to calculate the number of input capacitors, one must first determine the total rms input ripple current. to this end, begin by calculating the average input current to the converter: i in,avg i o,max d (5) where: d is the duty cycle of the converter, d = v out /v in ; is the specified minimum efficiency; i o,max is the maximum converter output current. the input capacitors will discharge when the control fet is on and charge when the control fet is off as shown in figure 21. the following equations will determine the maximum and minimum currents delivered by the input capacitors: i c,max i lo,max i in,avg (6) i c,min i lo,min i in,avg (7) i lo,max is the maximum output inductor current: i lo,max i o,max 4 i lo 2 (8) i lo,min is the minimum output inductor current: i lo,min i o,max 4 i lo 2 (9) i lo is the peak ? to ? peak ripple current in the output inductor of value lo: i lo (v in v out ) d (lo f sw ) (10) for the four ? phase converter, the input capacitor(s) rms current is then: i cin,rms [4d (i c,min 2 i c,min i c,in i c , in 2 3) i in , avg 2 (1 4d)] 1 2 (11) select the number of input capacitors (n in ) to provide the rms input current (i cin,rms ) based on the rms ripple current rating per capacitor (i rms,rated ): n in i cin,rms i rms,rated (12) for a four ? phase converter with perfect efficiency ( = 1), the worst case input ripple ? current will occur when the converter is operating at a 12.5% duty cycle. at this operating point, the parallel combination of input capacitors must support an rms ripple current equal to 12.5% of the converter?s dc output current. at other duty cycles, the ripple ? current will be less. for example, at a duty cycle of either 6% or 19%, the four ? phase input ripple ? current will be approximately 10% of the converter?s dc output current. in general, capacitor manufacturers require derating to the specified ripple ? current based on the ambient temperature. more capacitors will be required because of the current derating. the designer should know the esr of the input capacitors. the input capacitor power loss can be calculated from: p cin i cin,rms 2 esr_per_capacitor n in (13) low esr capacitors are recommended to minimize losses and reduce capacitor heating. the life of an electrolytic capacitor is reduced 50% for every 10 c rise in the capacitor?s temperature. i c,max i c,min 0 a ? i in,avg fet on, caps discharging fet off, caps charging t on t/4 i c,in = i c,max ? i c,min figure 21. input capacitor current for a four ? phase converter
cs5307 http://onsemi.com 18 + + vi 12 v li tbd n ci ci esr ci /n ci q2 q1 lo esr co /n co 14 u(t) n co co vi(t = 0) = 12 v swnode vo(t = 0) = 1.5 v v ci i lo v out i li max di/dt occurs in first few pwm cycles. figure 22. calculating the input inductance + ? 4. input inductor selection the use of an inductor between the input capacitors and the power source will accomplish two objectives. first, it will isolate the voltage source and the system from the noise generated in the switching supply. second, it will limit the inrush current into the input capacitors at power up. large inrush currents reduce the expected life of the input capacitors. the inductor?s limiting effect on the input current slew rate becomes increasingly beneficial during load transients. the worst case input current slew rate will occur during the first few pwm cycles immediately after a step ? load change is applied as shown in figure 22. when the load is applied, the output voltage is pulled down very quickly. current through the output inductors will not change instantaneously, so the initial transient load current must be conducted by the output capacitors. the output voltage will step downward depending on the magnitude of the output current (i o,max ), the per capacitor esr of the output capacitors (esr out ) and the number of the output capacitors (n out ) as shown in figure 22 . assuming the load current is shared equally between the four phases, the output voltage at full transient load will be: v out,full ? load (14) v out,no ? load (i o,max 4) esr out n out when the control mosfet (q1 in figure 22) turns on, the input voltage will be applied to the opposite terminal of the output inductor (the swnode). at that instant, the voltage across the output inductor can be calculated as: v lo v in v out,full ? load (15) v in v out,no ? load (i o,max 4) esr out n out the differential voltage across the output inductor will cause its current to increase linearly with time. the slew rate of this current can be calculated from: di lo dt v lo lo (16) current changes slowly in the input inductor so the input capacitors must initially deliver the vast majority of the input current. the amount of voltage drop across the input capacitors ( v ci ) is determined by the number of input capacitors (n in ), their per capacitor esr (esr in ) and the current in the output inductor according to: v ci esr in n in di lo dt t on esr in n in di lo dt d f sw (17) before the load is applied, the voltage across the input inductor (v li ) is very small and the input capacitors charge to the input voltage v in . after the load is applied, the voltage drop across the input capacitors, v ci , appears across the input inductor as well. knowing this, the minimum value of the input inductor can be calculated from: li min v li di in dt max v ci di in dt max (18) di in /dt max is the maximum allowable input current slew rate. the input inductance value calculated from equation 18 is relatively conservative. it assumes the supply voltage is very ?stiff? and does not account for any parasitic elements that will limit di/dt such as stray inductance. also, the esr values of the capacitors specified by the manufacturer?s data sheets are worst case high limits. in reality, input voltage ?sag,? lower capacitor esrs and stray inductance will help reduce the slew rate of the input current.
cs5307 http://onsemi.com 19 as with the output inductor, the input inductor must support the maximum current without saturating the inductor. also, for an inexpensive iron powder core, such as the ? 26 or ? 52 from micrometals, the inductance ?swing? with dc bias must be taken into account and inductance will decrease as the dc input current increases. at the maximum input current, the inductance must not decrease below the minimum value or the di/dt will be higher than expected. 5. mosfet & heatsink selection power dissipation, package size and thermal requirements drive mosfet selection. to adequately size the heat sink, the design must first predict the mosfet power dissipation. once the dissipation is known, the heat sink thermal impedance can be calculated to prevent the specified maximum case or junction temperatures from being exceeded at the highest ambient temperature. power dissipation has two primary contributors: conduction losses and switching losses. the control or upper mosfet will display both switching and conduction losses. the synchronous or lower mosfet will exhibit only conduction losses because it switches into nearly zero voltage. however, the body diode in the synchronous mosfet will suffer diode losses during the non ? overlap time of the gate drivers. for the upper or control mosfet, the power dissipation can be approximated from: p d,control (i rms,cntl 2 r ds(on) ) (i lo,max q switch i g v in f sw ) (q oss 2 v in f sw ) (v in q rr f sw ) (19) the first term represents the conduction or ir losses when the mosfet is on while the second term represents the switching losses. the third term is the loss associated with the control and synchronous mosfet output charge when the control mosfet turns on. the output losses are caused by both the control and synchronous mosfet but are dissipated only in the control fet. the fourth term is the loss due to the reverse recovery time of the body diode in the synchronous mosfet. the first two terms are usually adequate to predict the majority of the losses. i rms,cntl is the rms value of the trapezoidal current in the control mosfet: (20) i rms,cntl d [(i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 i lo,max is the maximum output inductor current: i lo,max i o,max 4 i lo 2 (21) i lo,min is the minimum output inductor current: i lo,min i o,max 4 i lo 2 (22) i o,max is the maximum converter output current. i d v gate v drain q gd q gs2 q gs1 v gs_th figure 23. mosfet switching characteristics d is the duty cycle of the converter: d v out v in (23) i lo is the peak ? to ? peak ripple current in the output inductor of value l o : i lo (v in v out ) d (lo f sw ) (24) r ds(on) is the on resistance of the mosfet at the applied gate drive voltage. q switch is the post gate threshold portion of the gate ? to ? source charge plus the gate ? to ? drain charge. this may be specified in the data sheet or approximated from the gate ? charge curve as shown in the figure 23. q switch q gs2 q gd (25) i g is the output current from the gate driver ic. v in is the input voltage to the converter. f sw is the switching frequency of the converter. q g is the mosfet total gate charge to obtain r ds(on) . commonly specified in the data sheet. v g is the gate drive voltage. q rr is the reverse recovery charge of the lower mosfet. q oss is the mosfet output charge specified in the data sheet. for the lower or synchronous mosfet, the power dissipation can be approximated from: p d,synch (i rms,synch 2 r ds(on) ) (vf diode i o,max 4 t_nonoverlap f sw ) (26) the first term represents the conduction or ir losses when the mosfet is on and the second term represents the diode losses that occur during the gate non ? overlap time. all terms were defined in the previous discussion for the control mosfet with the exception of: (27) i rms,synch 1 d [(i lo,max 2 i lo,max i lo,min i lo,min 2 ) 3] 1 2 where:
cs5307 http://onsemi.com 20 vf diode is the forward voltage of the mosfet?s intrinsic diode at the converter output current. t_nonoverlap is the non ? overlap time between the upper and lower gate drivers to prevent cross conduction. this time is usually specified in the data sheet for the control ic. when the mosfet power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case ambient operating temperature. t
(t j t a ) p d (28) where: t is the total thermal impedance ( jc + sa ); jc is the junction ? to ? case thermal impedance of the mosfet; sa is the sink ? to ? ambient thermal impedance of the heatsink assuming direct mounting of the mosfet (no thermal ?pad? is used); t j is the specified maximum allowed junction temperature; t a is the worst case ambient operating temperature. for to ? 220 and to ? 263 packages, standard fr ? 4 copper clad circuit boards will have approximate thermal resistances ( sa ) as shown below: pad size (in 2 /mm 2 ) single ? sided 1 oz. copper 0.50/323 60 ? 65 c/w 0.75/484 55 ? 60 c/w 1.00/645 50 ? 55 c/w 1.50/968 45 ? 50 c/w as with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading and component variations (i.e., worst case mosfet r ds(on) ). also, the inductors and capacitors share the mosfet?s heatsinks and will add heat and raise the temperature of the circuit board and mosfet. for any new design, it is advisable to have as much heatsink area as possible. all too often, new designs are found to be too hot and require re ? design to add heatsinking. 6. adaptive voltage positioning there are two resistors that determine the adaptive voltage positioning: r fb and r drp . r fb establishes the no ? load ?high? voltage position and r drp determines the full ? load ?droop? voltage. resistor r fb is connected between v core and the v fb pin of the controller. at no load, this resistor will conduct the internal bias current of the v fb pin and develop a voltage drop from v core to the v fb pin. because the error amplifier regulates v fb to the dac setting, the output voltage, v core , will be lower by the amount ibias vfb ? r fb . this condition is shown in figure 24. to calculate r fb , the designer must specify the no ? load voltage decrease below the vid setting ( v no ? load ) and determine the v fb bias current. usually, the no ? load voltage increase is specified in the design guide for the processor that is available from the manufacturer. the v fb bias current is determined by the value of the resistor from r osc to ground (see figure 4 in the data sheet for a graph of ibias vfb versus r osc ). the value of r fb can then be calculated: r fb v no ? load ibias vfb (29) ? + + ? r cs1 cs1 c cs1 l1 0 a g vdrp + ? r csx csx c csx lx 0 a g vdrp cs ref comp error amp vid setting ibias vfb r drp r fb v drp = vid v fb = vid v core i drp = 0 i fb = ibias vfb v core = vid + ibias vfb r fb figure 24. avp circuitry at no ? load + ?
cs5307 http://onsemi.com 21 ? + + ? r cs1 cs1 c cs1 l1 i max /2 g vdrp + ? r csx csx c csx lx i max /2 g vdrp cs ref comp error amp vid setting ibias vfb r drp r fb v drp = vid + i max ? r l ? g vdrp v fb = vid v core i drp i fb v core = vid ? (i drp ? ibias vfb ) r fb figure 25. avp circuitry at full ? load i drp = i max ? r l ? g vdrp /r drp i fbk = i drp ? ibias vfb = vid ? i max r l g vdrp r fb /r drp + ibias vfb r fb + ? figure 26. v drp tuning waveforms. the rc time constant of the current sense network is too long (slow): v drp and v out respond too slowly. figure 27. v drp tuning waveforms. the rc time constant of the current sense network is too short (fast): v drp and v out both overshoot. resistor r drp is connected between the v drp and the v fb pins. at no ? load, the v drp and the v fb pins will both be at the dac voltage. this resistor will conduct zero current. however, at full ? load, the voltage at the v drp pin will increase proportional to the output inductor?s current while v fb will still be regulated to the dac voltage. current will be conducted from v drp to v fb by r drp . this current will be large enough to supply the v fb bias current and cause a voltage drop from v fb to v core across r fb . the converter?s output voltage will be reduced. this condition is shown in figure 25. to determine the value of r drp , the designer must specify the full ? load voltage reduction from the vid (dac) setting ( v out,full ? load ) and predict the voltage increase at the v drp pin at full ? load. usually, the full ? load voltage reduction is specified in the design guide for the processor that is available from the manufacturer. to predict the voltage increase at the v drp pin at full ? load ( v drp ), the designer must consider the output inductor?s resistance (r l ), the pcb trace resistance between the current sense points (r pcb ) and the controller ic?s gain from the current sense to the v drp pin (g vdrp ): v drp i o,max (r l r pcb ) g vdrp (30) the value of r drp can then be calculated: r drp v drp (ibias vfb v out , full ? load r fb ) (31) v out,full ? load is the full ? load voltage reduction from the vid (dac) setting. vout,full ? load is not the voltage change from the no ? load avp setting. 7. current sensing for inductive current sensing, choose the current sense network (r csx , c csx , x = 1, 2, 3, or 4) to satisfy r csx c csx lo (r l r pcb ) (32)
cs5307 http://onsemi.com 22 figure 28. v drp tuning waveforms. the rc time constant of the current sense network is optimal: v drp and v out respond to the load current quickly without overshooting. figure 29. the value of c amp is too high and the loop gain/bandwidth too low. comp slews too slowly which results in overshoot in v out . for resistive current sensing, choose the current sense network (r csx , c csx , x = 1, 2, 3, or 4) to satisfy r csx c csx lo (r sense ) (33) this will provide an adequate starting point for r csx and c csx . after the converter is constructed, the value of r csx (and/or c csx ) should be fine ? tuned in the lab by observing the v drp signal during a step change in load current. tune the r csx ? c csx network to provide a ?square ? wave? at the v drp output pin with maximum rise time and minimal overshoot as shown in figure 28. 8. error amplifier tuning after the steady ? state (static) avp has been set and the current sense network has been optimized, the error amplifier must be tuned. the gain of the error amplifier should be adjusted to provide an acceptable transient response by increasing or decreasing the error amplifier?s feedback capacitor (c amp in the applications diagram). the bandwidth of the control loop will vary directly with the gain of the error amplifier. if c amp is too lar ge, the loop gain/bandwidth will be low, the comp pin will slew too slowly and the output voltage will overshoot as shown in figure 29. on the other hand, if c amp is too small, the loop gain/bandwidth will be high, the comp pin will slew very quickly and overshoot will occur. integrator ?wind up? is the cause of the overshoot. in this case, the output voltage will transition more slowly because comp spikes upward as shown in figure 30. t oo much loop gain/bandwidth increases the risk of instability. in general, one should use the lowest loop gain/bandwidth possible to achieve acceptable transient response. this will ins ure good stability. if c amp is optimal, the comp pin will slew quickly but not overshoot and the output voltage will monotonically settle as shown in figure 32. after the control loop is tuned to provide an acceptable transient response, the steady ? state voltage ripple on the comp pin should be examined. when the converter is operating at full steady ? state load, the peak ? to ? peak voltage ripple (v pp ) on the comp pin should be less than 20 mv pp as shown in figure 31. less than 10 mv pp is ideal. excessive ripple on the comp pin will contribute to jitter. 9. current limit setting when the output of the current sense amplifier (cox in the block diagram) exceeds the voltage on the i lim pin, the part will enter hiccup mode. for inductive sensing, the ocset pin voltage should be set based on the inductor?s maximum resistance (r lmax ). the design must consider the inductor?s resistance increase due to current heating and ambient temperature rise. also, depending on the current sense points, the circuit board may add additional resistance. in general, the temperature coefficient of copper is +0.39% per c. if using a current sense resistor (r sense ), the ocset pin voltage should be set based on the maximum value of the sense resistor. to set the level of the ocset pin: figure 30. the value of c amp is too low and the loop gain/bandwidth too high. comp moves too quickly, which is evident from the small spike in its voltage when the load is applied or removed. the output voltage transitions more slowly because of the comp spike.
cs5307 http://onsemi.com 23 figure 31. at full ? load the peak ? to ? peak voltage ripple on the comp pin should be less than 20 mv for a well ? tuned/stable controller. higher comp voltage ripple will contribute to output voltage jitter. figure 32. the value of c amp is optimal. comp slews quickly without spiking or ringing. v out does not overshoot and monotonically settles to its final value. v ocset (i out,lim i lo 2) r g ilim (34) where: i out,lim is the current limit threshold of the converter; i lo /2 is half the inductor ripple current; r is either (r lmax + r pcb ) or r sense; g ilim is the current sense to ocset gain. for the overcurrent protection to work properly, the current sense time constant (rc) should be slightly larger than the r l time constant. if the rc time constant is too fast, a step load change will cause the sensed current waveform to appear larger than the actual inductor current and will trip the current limit at a lower level than expected. 10. pwm comparator input voltage the voltage at the positive input terminal of the pwm comparator (see figure 14 or 16) is limited by the internal voltage supply of the controller (3.3 v), the size of the internal ramp and the magnitude of the channel startup of fset voltage. to prevent the pwm comparator from saturating, the differential input voltage from cs ref to csn (n = 1, 2, 3, or 4) must satisfy the following equation: v csref,max v cox,max 600 mv d 2.45 v (35) where: v csref,max max vid setting w avp @ full load v con,max [v csx v csref ] g csa,max (i o,max 2 i lo 2) r max g csa,max r max r sense or (r l,max r pcb,max ) 11. soft start time the soft start time (t ss ) can be calculated from: c ss v comp channel_startup_offset 160 a (36) t ss c ss v i ss where: 2.353 v dc (from page 12) v comp v out @0a channel_startup_offset int_ramp g csa ext_ramp 2 if c ss = 0.1 f, then the soft start time will be: t ss 0.1 f 1.753 v dc 160 a 1.1 ms (37) the channel_startup_offset is subtracted from v comp as the output does not begin to rise until v comp exceeds this voltage. as the internal and external ramp values are small, the soft start time may be approximated by: t ss c ss v out @0a i ss (38)
cs5307 http://onsemi.com 24 package dimensions so ? 24l dw suffix case 751e ? 04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? a ? ? b ? p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t ? t ? g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 cs5307/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative v 2 is a trademark of switch power, inc.

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